Automated Design Space Exploration for RISC-V CVA6
Our AutoML platform enables rapid exploration of the performance-power trade-offs in RISC-V CVA6 processors using Dhrystone benchmark metrics. Optimize your processor configuration with machine learning predictions.
Key Design Space Metrics
Performance
Dhrystone MIPS (DMIPS) and IPC (Instructions Per Cycle) metrics across different configurations.
Power Efficiency
Power consumption (mW) and energy per instruction (EPI) measurements.
Microarchitecture
Pipeline depth, cache sizes, branch prediction, and other key parameters.
Design Space Explorer
Configuration Parameters
Performance-Power Trade-off
Pareto Frontier Analysis
AutoML Prediction Engine
Optimization Target
Recommended Configuration
About This Project
This AutoML platform for RISC-V CVA6 Design Space Exploration (DSE) was developed to help computer architects and hardware designers quickly evaluate performance-power trade-offs using the Dhrystone benchmark.
Methodology
Our system uses machine learning models trained on extensive simulation data to predict processor metrics across the design space without requiring time-consuming RTL simulations for every configuration.
Technical Details
- Based on the open-source CVA6 (formerly Ariane) RISC-V core
- Dhrystone benchmark as the performance metric
- Power estimation using industry-standard models
- Gradient boosting and neural network prediction models
- Multi-objective optimization for Pareto frontier analysis
Get Involved
This is an open-source project. Contributions are welcome!
